From multi-camera phones and in-vehicle screens to embedded-AI terminals, how can these devices “see clearly and show quickly”?

—— MIPI D-PHY

MIPI D-PHY is a high-speed serial physical-layer interface defined by the MIPI Alliance. It is widely used for Camera Serial Interface (CSI-2), Display Serial Interface (DSI) and any scenario that demands high-speed yet low-power links. Employing source-synchronous differential signaling, it offers both Low-Power (LP) and High-Speed (HS) modes on the same lane, enabling bi-directional or uni-directional transport.

Display Serial Interface (DSI)

DSI is the MIPI Alliance’s high-speed serial display protocol between a host processor and a display module. It rides on MIPI D-PHY (or C-PHY) to deliver high-bandwidth, low-power video over a small pin count.

Layer stack

Application: image formats, virtual channels (VC)

Protocol: Long packets (pixel data), Short packets (control/status), Escape/ULPS low-power modes

Physical: D-PHY (or C-PHY) clock lane + 1–4 (up to 8) data lanes

Key specs

Version: mainstream v1.3; v2.0 emerging (e.g., RK3576)

Lanes: 1 / 2 / 4 / 8; phones usually 2-lane, high-res panels 4-lane

Rate: v1.3 2.0–2.5 Gbps/lane; v2.0 up to 3.5 Gbps/lane → 4-lane ≈ 10 Gbps

Pixel throughput: 2-lane 2.5 Gbps ≈ 200 Mpix/s (RGB888) or 333 Mpix/s (RAW10)

Formats: RAW8/10/12/14, RGB565/888, YUV422/420 (all CSI-2/DSI defined)

Virtual channels: 4 (v1.3) or 8 (v2.0)

Low-power states: LP, Escape, ULPS

Example chips

RK3576: 3 MIPI CSI-2, two 4-lane D-PHY v1.2 (splittable 2×2), one 4-lane C/D-PHY; D-PHY v2.0 @ 4.5 Gbps/lane

RK3588: 2 MIPI DC-PHY (D-PHY or C-PHY), each D-PHY v1.2 4-lane 2.5 Gbps/lane

Camera Serial Interface (CSI-2)

CSI-2 is the MIPI Alliance standard for high-speed camera-to-host transport of RAW, YUV or RGB data over D-PHY or C-PHY differential links.

Architecture

PHY: 100 Ω ± 20 % differential impedance, terminated; HS/LP mode switching with strict sequence (LP-11→LP-01→LP-00→HS-EN)

Lane management: byte-wise round-robin striping across lanes for parallel throughput

Protocol:(Long/Short packets)

Application: pixel formats & DCS commands

Key specs

Lanes: 1 / 2 / 4 (mainstream) or 8 (premium); dedicated clock lane

Rate: v1.3 2.0–2.5 Gbps/lane; v2.0 (2024-25) 3.5 Gbps/lane → 4-lane ≈ 14 Gbps

Pixel throughput: 2-lane 2.5 Gbps ≈ 200 Mpix/s (RGB888), 333 Mpix/s (RAW10)

Virtual channels: 4 (v1.3) or 8 (v2.0) for concurrent streams/metadata

Formats: RGB565/888, YUV422/420, RAW8/10/12/14

Compression: VESA DSC optional for 4K@60 Hz / 8K@30 Hz bandwidth reduction